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| rev.1.0 data sheet no. pd60347a irs26310djpbf high voltage 3 phase gate driver ic with dc bus over Cvoltage protection features ? drives up to six igbt/mosfet power devices ? gate drive supplies up to 20 v per channel ? integrated bootstrap functionality ? dc bus sensing with over voltage protection ? overcurrent protection ? overtemperature shutdown input ? advanced input filter ? integrated deadtime protection ? shootthrough (crossconduction) protection ? under voltage lockout for v cc & v bs ? enable/disable input and fault reporting ? adjustable fault clear timing ? separate logic and power grounds ? 3.3 v input logic compatible ? tolerant to negative transient voltage ? designed for use with bootstrap power supplies ? matched propagation delays for all channels ? 40 c to 125 c operating range ? rohs compliant typical applications ? permanent magnet motor drives for appliances ? industrial drives ? micro inverter drives product summary topology 3 phase v offset 600 v v out 12 v C 20 v i o+ & i o (typical) 200 ma & 350 ma t on & t off (typical) 530 ns & 530 ns deadtime (typical) 290 ns package options 44lead plcc (without 12 leads) typical connection diagram
irs26310djpbf www.irf.com ? 2007 international rectifier 2 table of contents page description 3 simplified block diagram 3 typical application diagram 4 qualification information 5 absolute maximum ratings 6 recommended operating conditions 7 static electrical characteristics 8 dynamic electrical characteristics 10 functional block diagram 11 input/output pin equivalent circuit diagram 12 lead definitions 13 lead assignments 14 application information and additional details 15 parameter temperature trends 36 package details 40 tape and reel details 41 part marking information 42 ordering information 43 irs26310djpbf www.irf.com ? 2007 international rectifier 3 description the irs26310djpbf is a high voltage, high speed pow er mosfet and igbt driver with three independent high and low side referenced output channels for 3 phase applications. this ic is designed to be used with lowcost bootstrap power supplies; the bootstrap di ode functionality has been integrated into this dev ice to reduce the component count and the pcb size. propri etary hvic technology enables ruggedized monolithic construction. logic inputs are compatible with cmos or lsttl outputs, down to 3.3v logic. a current tr ip function which terminates all six outputs can be de rived from an external current sense resistor. an e nable function is available to terminate all six outputs simultaneously. an opendrain fault signal is provi ded to indicate that an overcurrent or a vcc undervoltage shutdown has occurred. overcurrent fault conditions are cleared automatically after a delay programmed exte rnally via an rc network connected to the rcin inpu t. the output drivers feature a high pulse current buf fer stage designed for minimum driver crossconduct ion. propagation delays are matched to simplify use in h igh frequency applications. the floating channel ca n be used to drive nchannel power mosfets or igbts in t he high side configuration which operates up to 600 v. a dcbus sensing is provided using an external divid er. over voltage dcbus protection is activate when dcbus exceed an externally adjustable threshold, ac tivating zerovector braking mode (all low side out put turnon, all high side outputturnoff). simplified block diagram irs26310djpbf www.irf.com ? 2007 international rectifier 4 typical application diagram irs26310djpbf www.irf.com ? 2007 international rectifier 5 qualification information ? industrial ?? qualification level comments: this family of ics has passed jedecs industrial qualification. irs consumer qualificat ion level is granted by extension of the higher industrial level . moisture sensitivity level plcc44 msl3 ??? , 245 c (per ipc/jedec jstd020) machine model class b (per jedec standard jesd22a114) human body model class 2 (per eia/jedec standard eia/jesd22a115) esd charged device model class iv (per jedec standard jesd22c101) ic latch-up test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales representative for fu rther information. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative for fu rther information. irs26310djpbf www.irf.com ? 2007 international rectifier 6 absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all v oltage parameters are absolute voltages referenced to v ss unless otherwise stated in the table. the thermal resistance and power dissipation ratings are measured under bo ard mounted and still air conditions. voltage clam ps are included between v cc & com (25 v), v cc & v ss (20 v), and v b & v s (20 v). symbol definition min. max. units v s high side offset voltage v b 20 ? v b + 0.3 v tst tst voltage 0.3 20 v b high side floating supply voltage 0.3 620 v ho high side floating output voltage v s 0.3 v b + 0.3 v cc low side and logic fixed supply voltage 0.3 20 v ss logic ground v cc 20 v cc + 0.3 v lo1,2,3 low side output voltage 0.3 v cc + 0.3 v in input voltage lin, hin, itrip, en, rcin v ss 0.3 v cc + 0.3 v flt fault output voltage v ss 0.3 v cc + 0.3 v dcbussense input sensing for dc bus voltage v ss 0.3 v cc + 0.3 v dv/dt allowable offset voltage slew rate 50 v/ns p d package power dissipation @ ta +25c 2 w rth ja thermal resistance, junction to ambient 63 c/w t j junction temperature 150 t s storage temperature 55 150 t l lead temperature (soldering, 10 seconds) 300 c ? all supplies are fully tested at 25 v. an internal 20 v clamp exists for each supply. irs26310djpbf www.irf.com ? 2007 international rectifier 7 recommended operating conditions for proper operation, the device should be used wit hin the recommended conditions. all voltage parame ters are absolute voltages referenced to v ss unless otherwise stated in the table. the offset rating is tested with supplies of (v cc com) = (v b v s ) = 15 v. symbol definition min. max. units v b high side floating supply voltage v s +12 v s + 20 v s high side floating supply voltage ? com8 600 v s (t) transient highside floating supply voltage ?? 50 600 v tst tst voltage 12 20 v cc low side supply voltage 12 20 v ho high side output voltage v s v b v lo low side output voltage 0 v cc v ss logic ground 5 5 v flt fault output voltage v ss v cc v rcin rcin input voltage v ss v cc v itrip itrip input voltage v ss v ss + 5 v in logic input voltage lin, hin, en v ss v ss + 5 v dcbussense input sensing for dcbus voltage ??? v ss v cc v t a ambient temperature 40 125 c ? logic operation for v s of C8 v to 600 v. logic state held for v s of C8 v to Cv bs . please refer to design tip dt973 for more details. ?? operational for transient negative v s of v ss 50 v with a 50 ns pulse width. guaranteed by design. ref er to the application information section of this datashe et for more details. ??? dcbussense pin is internally clamped with a 10.4 v zener diode. irs26310djpbf www.irf.com ? 2007 international rectifier 8 static electrical characteristics (v cc com) = (v b v s ) = 15 v. t a = 25 o c unless otherwise specified. the v in ,v th and i in parameters are referenced to v ss and are applicable to all six channels. the v o and i o parameters are referenced to respective v s and com and are applicable to the respective output leads ho or lo. the v ccuv parameters are referenced to v ss . the v bsuv parameters are referenced to v s . symbol definition min. typ. max. units test conditions v ih logic 1 input 2.5 v il logic 0 input 0.8 v in , th+ input positive going threshold 1.9 v in , th input negative going threshold 1 v en,th+ enable positive going threshold 2.5 v en,th enable negative going threshold 0.8 v it,th+ itrip positive going threshold 0.37 0.46 0.55 v it,hys itrip hysteresis 0.05 0.07 v rcin, th+ rcin positive going threshold 8 v rcin, hys rcin hysteresis 3 v oh high level output voltage, v bias C v o 1.12 1.74 v ol low level output voltage, v o 0.4 0.6 i o = 20 ma v ccuv+ v cc supply undervoltage positive going threshold 10.4 11.1 11.6 v ccuv v cc supply undervoltage negative going threshold 10.2 10.9 11.4 v ccuvhys v cc supply undervoltage hysteresis 0.17 0.2 v bsuv+ v bs supply undervoltage positive going threshold 10.4 11.1 11.6 v bsuv v bs supply undervoltage negative going threshold 10.2 10.9 11.4 v bsuvhy v bs supply undervoltage hysteresis 0.17 0.2 v dcbussth+ over voltage dcbussense positive going threshold 3.86 4.20 4.54 v dcbussth over voltage dcbussense negative going threshold 3.70 4.03 4.35 v dcbusshys over voltage dcbussense hysteresis 0.14 0.17 v note 1 i lk offset supply leakage current 3 50 v b =v s = 600 v i qbs quiescent v bs supply current 50 120 i qcc quiescent v cc supply current 3 4 ma all inputs @ logic 0 value i in+ input bias current (lo or ho= high) 100 150 v in = 3.3 v i in input bias current (lo or ho = low) 1 0 v in = 0 v i itrip+ high itrip input bias current 5 40 v itrip = 5 v i itrip low itrip input bias current 1 0 v itrip = 0 v i flt/en+ high flt/enable input bias current 0 1 v flt/en = 3.3 v i flt/en low flt/enable input bias current 1 0 v flt/en = 0 v i dcbussense+ high dcbussense input bias current 0 1 v dcbsense = 5 v i dcbussense low dcbussense input bias current 1 0 ua v dcbsense = 0 v note 1 : guaranteed by design over a temperature range of 0o c to 110oc irs26310djpbf www.irf.com ? 2007 international rectifier 9 static electrical characteristics (continued) (v cc com) = (v b v s ) = 15 v. t a = 25 o c unless otherwise specified. the v in ,v th and i in parameters are referenced to v ss and are applicable to all six channels. the v o and i o parameters are referenced to respective v s and com and are applicable to the respective output leads ho or lo. the v ccuv parameters are referenced to v ss . the v bsuv parameters are referenced to v s . symbol definition min. typ. max. units test conditions i rcin+ high rcin input bias current 0 1 v rcin = 15 v i rcin low rcin input bias current 1 0 ua v rcin = 0 v io+ output high short circuit pulsed current 120 20 0 vo = 0 v, pw 10 s io output low short circuit pulsed current 250 350 ma vo = 15 v, pw 10 s r on_rcin rcin low on resistance 50 100 r on_faulten fault low on resistance 50 100 i = 1.5 ma r bs internal bootstrap diode ron 200 400 irs26310djpbf www.irf.com ? 2008 international rectifier 10 dynamic electrical characteristics v cc = v b = 15 v, v s = v ss = com, t a = 25 o c, and c l = 1000 pf unless otherwise specified. symbol definition min. typ. max. units test conditi ons t on turnon propagation delay 400 530 750 t off turnoff propagation delay 400 530 750 t r turnon rise time 125 190 t f turnoff fall time 50 75 v in = 0v & 5v t itrip itrip to output shutdown propagation delay 500 750 1200 v itrip = 5v t itrip_blk itrip blanking time 500 750 t flt itrip to fault propagation delay 400 600 950 v in = 0v & 5v v itrip = 5v t enout enable high to output propagation delay 350 460 650 t sdout enable low to output shutdown propagation delay 350 460 650 v in = 0v & 5v v en = 0v & 3.3v t zv _ dcbs_loon dcbussense entering over voltage to lo turn on 310 460 730 t zv _ dcbs_hooff dcbussense entering over voltage to ho turn off 310 460 730 t zv _ dcbs_hoon dcbussense exiting over voltage to ho turn on 270 380 590 t zv _ dcbs_looff dcbussense exiting over voltage to lo turn off 300 450 720 t zv_dcbs_flt_lo dcbussense input filter time on lo 140 250 420 t zv_dcbs_flt_ho dc bus s ense input filter time on ho 140 250 420 ns v dcbsense = 0v & 5v t filin input filter time (hin, lin) ? 200 350 510 v in = 0v & 5v t filteren enable input filter time 100 200 dt deadtime 190 290 420 mt ton, toff matching time (on all six channels) 50 mdt dt matching (hin>lo & lo >hin on all channels) 60 v in = 0v & 5v external dead time 0s pm pulse width distortion ?? 75 ns pw input =10s t fltclr fault clear time rcin: r = 2 meg, c = 1nf 1.3 1.65 2 ms v in = 0v or 5v v itrip = 0v ? the minimum width of the input pulse is recommended to exceed 500 ns to ensure the filtering time of t he input filter is exceeded. ?? pm is defined as pw in pw out . irs26310djpbf www.irf.com ? 2008 international rectifier 11 functional block diagram: irs26310dj irs26310djpbf www.irf.com ? 2008 international rectifier 12 input/output pin equivalent circuit diagrams: irs26310d esd diode esd diode v cc hin lin v ss r pd 20 v clamp esd diode esd diode v cc dcbus sense v ss 10.4v clamp esd diode esd diode v b ho v s esd diode esd diode lo com 600 v 20 v clamp 25 v clamp v cc v ss tst irs26310djpbf www.irf.com ? 2008 international rectifier 13 lead definitions: irs26310dj symbol description vcc lowside supply voltage vss logic ground tst tst to be shorted to vcc vb1 highside gate drive floating supply (phase 1) vb2 highside gate drive floating supply (phase 2) vb3 highside gate drive floating supply (phase 3) vs1 high voltage floating supply return (phase 1) vs2 high voltage floating supply return (phase 2) vs3 high voltage floating supply return (phase 3) hin1 logic inputs for highside gate driver outputs (phase 1) hin2 logic inputs for highside gate driver outputs (phase 2) hin3 logic inputs for highside gate driver outputs (phase 3 lin1 logic inputs for lowside gate driver outputs (phase 1) lin2 logic inputs for lowside gate driver outputs (phase 2) lin3 logic inputs for lowside gate driver outputs (phase 3) ho1 highside driver outputs (phase 1) ho2 highside driver outputs (phase 2) ho3 highside driver outputs (phase 3) lo1 lowside driver outputs (phase 1) lo2 lowside driver outputs (phase 2) lo3 lowside driver outputs (phase 3) com lowside gate drive return fault/n en indicates overcurrent, overtemperature (itrip), o r lowside undervoltage lockout has occurred. this pin has negative logic and an opendrain outpu t. the use of overcurrent and over temperature protection requires the use of external components. logic input to shutdown functionality. logic functi ons when en is high (i.e., positive logic). no effect on fault and not latched. itrip analog input for overcurrent shutdown. when active , itrip shuts down outputs and activates fault and rcin low. when itrip becomes inactive, f ault stays active low for an externally set time t fltclr , then automatically becomes inactive (opendrain h igh impedance). dcbussense analog input for dcbus sensing rcin an external rc network input used to define the fau lt clear delay (t fltclr ) approximately equal to r*c. when rcin > 8 v, the fault pin goes back into an opendrain highimpedance state. irs26310djpbf www.irf.com ? 2008 international rectifier 14 lead assignments irs26310djpbf www.irf.com ? 2008 international rectifier 15 application information and additional details informations regarding the following topics are inc luded as subsections within this section of the dat asheet. ? igbt/mosfet gate drive ? switching and timing relationships ? deadtime ? matched propagation delays ? input logic compatibility ? undervoltage lockout protection ? shootthrough protection ? enable input ? fault reporting and programmable fault clear timer ? overcurrent protection ? overtemperature shutdown protection ? dc bus overvoltage protection ? truth table: undervoltage lockout, itrip, and enab le ? advanced input filter ? shortpulse / noise rejection ? integrated bootstrap functionality ? bootstrap power supply design ? separate logic and power grounds ? tolerant to negative v s transients ? pcb layout tips ? bootstrap fet limitation ? additional documentation igbt/mosfet gate drive the irs26310d hvic is designed to drive up to six m osfet or igbt power devices. figures 1 and 2 illus trate several parameters associated with the gate drive f unctionality of the hvic. the output current of th e hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the highside power switch and v lo for the lowside power switch; this parameter is s ometimes generically called v out and in this case does not differentiate between th e highside or lowside output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + v s (or com) ho (or lo) v b (or v cc ) i o figure 1: hvic sourcing current figure 2: hvic sinking current irs26310djpbf www.irf.com ? 2008 international rectifier 16 switching and timing relationships the relationship between the input and output signa ls of the irs26310d is illustrated below in figures 3. from this figure, we can see the definitions of several timin g parameters (i.e., pw in , pw out , t on , t off , t r , and t f ) associated with this device. figure 3: switching time waveforms the following two figures illustrate the timing rel ationships of some of the functionality of the irs2 6310d; this functionality is described in further detail later in this document. during interval a of figure 4, the hvic has receive d the command to turnon both the high and lowsid e switches at the same time; as a result, the shootthrough prote ction of the hvic has prevented this condition and both the high and lowside output are held in the off state. interval b of figures 4 and 5 shows that the signal on the itrip input pin has gone from a low to a hi gh state; as a result, all of the gate drive outputs have been dis abled (i.e., see that hox has returned to the low s tate; lox is also held low), the voltage on the rcin pin has been pul led to 0 v, and a fault is reported by the fault ou tput transitioning to the low state. once the itrip inp ut has returned to the low state, the output will r emain disabled and the fault condition reported until the voltage on t he rcin pin charges up to v rcin,th (see interval c in figure 6); the charging characteristics are dictated by the rc net work attached to the rcin pin. during intervals d and e of figure 4, we can see th at the enable (en) pin has been pulled low (as is t he case when the driver ic has received a command from the contr ol ic to shutdown); this results in the outputs (ho x and lox) being held in the low state until the enable pin is pulled high. irs26310djpbf www.irf.com ? 2008 international rectifier 17 figure 4: input/output timing diagram 50% 90% 50% t fltclr t itrip t flt rcin itrip hox fault v rcin,th v it,th+ interval b interval c v it,th figure 5: detailed view of b & c intervals deadtime this family of hvics features integrated deadtime p rotection circuitry. the deadtime for these ics is fixed; other ics within irs hvic portfolio feature programmable dea dtime for greater design flexibility. the deadtime feature inserts a time period (a minimum deadtime) in which both th e high and lowside power switches are held off; t his is done to ensure that the power switch being turned off has f ully turned off before the second power switch is t urned on. this minimum deadtime is automatically inserter whenever the external deadtime is shorter than dt; external deadtimes larger than dt are not modified by the gate driver. figure 6 illustrates the deadtime period and the relationship between the output gate signals. the deadtime circuitry of the irs26310d is matched with respect to the high and lowside outputs of a given channel; additionally, the deadtimes of each of the three channels are matched. figure 6 defines the two deadtime parameters (i.e., dt 1 and dt 2 ) of a specific channel; the deadtime matching para meter (mdt) associated with the irs26310d specifies the maximum difference between dt 1 and dt 2 . the mdt parameter also applies when comparing the dt of one channel of the irs26310d to that of another. irs26310djpbf www.irf.com ? 2008 international rectifier 18 figure 6: illustration of deadtime matched propagation delays the irs26310d family of hvics is designed with prop agation delay matching circuitry. with this featur e, the ics response at the output to a signal at the input req uires approximately the same time duration (i.e., t on , t off ) for both the lowside channels and the highside channels; t he maximum difference is specified by the delay mat ching parameter (mt). additionally, the propagation dela y for each lowside channel is matched when compare d to the other lowside channels and the propagation delays of the highside channels are matched with each oth er; the mt specification applies as well. the propagation tur non delay (t on ) of the irs26310d is matched to the propagation turnon delay (t off ). input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the irs26310d has been desig ned to be compatible with 3.3 v and 5 v logiclevel signal s. figure 7 illustrates an input signal to the irs2 6310d, its input threshold values, and the logic state of the ic as a result of the input signal. figure 7: hin & lin input thresholds irs26310djpbf www.irf.com ? 2008 international rectifier 19 undervoltage lockout protection this family of ics provides undervoltage lockout pr otection on both the v cc (logic and lowside circuitry) power supply and the v bs (highside circuitry) power supply. figure 8 is u sed to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/ or v bsuv+/ ) the undervoltage protection is enabled or disabled. upon powerup, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turnon. additionally, if the v cc voltage decreases below the v ccuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition and shutdown the high and lowside gate drive outputs, and the fault pin will transit ion to the low state to inform the controller of the fault conditi on. upon powerup, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turnon. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition, and shutdown the highside gate drive ou tputs of the ic. the uvlo protection ensures that the ic drives the external power devices only when the gate supply vo ltage is sufficient to fully enhance the power devices. wit hout this feature, the gates of the external power switch could be driven with a low voltage, resulting in the power s witch conducting current while the channel impedanc e is high; this could result in very high conduction losses within the power device and could lead to power device fai lure. figure 8: uvlo protection shoot-through protection the irs26310d is equipped with shootthrough protec tion circuitry (also known as crossconduction prev ention circuitry). figure 9 shows how this protection cir cuitry prevents both the high and lowside switche s from conducting at the same time. table 1 illustrates the input/ou tput relationship of the devices in the form of a t ruth table. note that the irs26310d has noninverting inputs (the output is inphase with its respective input). irs26310djpbf www.irf.com ? 2008 international rectifier 20 figure 9: illustration of shoot-through protection circuitry irs26310dj hin lin ho lo 0 0 0 0 0 1 0 1 1 0 1 0 1 1 0 0 table 1: input/output truth table enable input the irs26310d is equipped with an enable input pin that is used to shutdown or enable the hvic. when the en pin is in the high state the hvic is able to operate no rmally (assuming no other fault conditions). when a condition occurs that should shutdown the hvic, the en pin sh ould see a low logic state. the enable circuitry o f the irs26310d features an input filter; the minimum inp ut duration is specified by t filter,en . please refer to the en pin parameters v en,th+ , v en,th , and i en for the details of its use. table 2 gives a summa ry of this pins functionality and figure 10 illustrates the outputs response to a sh utdown command. enable input enable input high outputs enabled * enable input low outputs disabled table 2: enable functionality truth table (*assumes no other fault condition) irs26310djpbf www.irf.com ? 2008 international rectifier 21 figure 10: output enable/disable timing waveform irs26310djpbf www.irf.com ? 2008 international rectifier 22 fault reporting and programmable fault clear timer the irs26310d family provides an integrated fault r eporting output and an adjustable fault clear timer . there are two situations that would cause the hvic to report a fa ult via the fault pin. the first is an undervoltag e condition of v cc and the second is if the itrip pin recognizes a fau lt. once the fault condition occurs, the fault pin is internally pulled to v ss and the fault clear timer is activated. the fault output stays in the low state until the fault cond ition has been removed and the fault clear timer expires; onc e the fault clear timer expires, the voltage on the fault pin will return to v cc . the length of the fault clear time period (t fltclr ) is determined by exponential charging characteris tics of the capacitor where the time constant is set by r rcin and c rcin . in figure 11 where we see that a fault condition has occurred (uvlo or itrip), rcin and fault are pulled to v ss , and once the fault has been removed, the fault cl ear timer begins. figure 12 shows that r rcin is connected between the v cc and the rcin pin, while c rcin is placed between the rcin and v ss pins. figure 11: rcin and fault pin waveforms figure 12: programming the fault clear timer the design guidelines for this network are shown in table 3. 1 nf c rcin ceramic 0.5 m to 2 m r rcin >> r on,rcin table 3: design guidelines the length of the fault clear time period can be de termined by using the formula below. v c (t) = v f (1e t/rc ) t fltclr = (r rcin c rcin )ln(1v rcin,th /v cc ) irs26310djpbf www.irf.com ? 2008 international rectifier 23 over-current protection the irs26310d hvics are equipped with an itrip inpu t pin. this functionality can be used to detect ov ercurrent events in the dc bus. once the hvic detects an ov ercurrent event through the itrip pin, the outputs are shutdown, a fault is reported through the fault pin , and rcin is pulled to v ss . the level of current at which the overcurrent prot ection is initiated is determined by the resistor n etwork (i.e., r 0 , r 1 , and r 2 ) connected to itrip as shown in figure 14, and the itrip threshold (v it,th+ ). the circuit designer will need to determine the maximum allowable level of current in the dc bus and select r 0 , r 1 , and r 2 such that the voltage at node v x reaches the overcurrent threshold (v it,th+ ) at that current level. v it,th+ = r 0 i dc (r 1 /(r 1 +r 2 )) figure 13: programming the over-current protection for example, a typical value for resistor r 0 could be 50 m. the voltage of the itrip pin shou ld not be allowed to exceed 5 v; if necessary, an external voltage clamp may be used. over-temperature shutdown protection the itrip input of the irs26310d can also be used t o detect overtemperature events in the system and initiate a shutdown of the hvic (and power switches) at that t ime. in order to use this functionality, the circu it designer will need to design the resistor network as shown in fig ure 14 and select the maximum allowable temperature . this network consists of a thermistor and two stand ard resistors r 3 and r 4 . as the temperature changes, the resistance of the thermistor will change; this will result in a change of voltage at node v x . the resistor values should be selected such the voltage v x should reach the threshold voltage (v it,th+ ) of the itrip functionality by the time that the maximum allowable temperature is reached. the voltage of the itrip pin should not be allowed to e xceed 5 v. when using both the overcurrent protection and ov ertemperature protection with the itrip input, or ing diodes (e.g., dl4148) can be used. this network is shown in figure 15; the oring diodes have been labeled d 1 and d 2 . irs26310djpbf www.irf.com ? 2008 international rectifier 24 figure 14: programming over-temperature protection figure 15: using over-current protection and over- temperature protection dc bus over-voltage protection when driving permanent magnet ac motors there is a potential to regenerate some of the motor mechanica l energy back onto the dc bus. zero vector braking prevents charging of the dc bus capacitor by shorti ng all three motor terminals to a common rail to dissipate this mechanical energy in the motor windings. the dc bus over voltage protection feature on the ic initiates zero vector braking when the dc bus voltage goes above some critical voltage level to prevent damage to dc bus components. zero vector braking should only be used when the motor winding inductance is sufficient to limit the motor short circuit current to a safe level. dc bu s protection operates even when all pwm inputs are disabled so w ill protect the motor when operating in high speed field weakening mode. the irs26310d ics have a dcbussense input pin to de tect overvoltage events on the dc bus. once the i c detects an overvoltage event, zero vector mode bra king is forced (all low side output turnon, all hi gh side outputturnoff) overriding the pwm signals coming from the controller. a fault is not reported on th e fault pin for this condition because the power inverter is st ill active. dc bus overvoltage protection is not l atched and so the zero vector mode is released when dcbussense pi n is lower than o vdcbusvth . the level of voltage at which the overvoltage prot ection is initiated is determined by the resistor d ivider (i.e., r 0 and r 1 ) connected to dcbussense as shown in figure 16, an d the dcbussense threshold (o vdcbusvth+ ). the circuit designer will need to determine the maximum allowab le level of dc bus voltage and select r 0 and r 1 such that the voltage at node v x reaches the overvoltage threshold (o vdcbusvth+ ). o vdcbusvth+ = r 1 v dcbus /(r 0 +r 1 ) irs26310djpbf www.irf.com ? 2008 international rectifier 25 r0 r1 dcbussense vss dcbus vx figure 16: programming the dc bus over-voltage prot ection truth table: undervoltage lockout, itrip, and enabl e table 4 provides the truth table for the irs26310d. the first line shows that the uvlo for v cc has been tripped; the fault output has gone low and the gate drive output s have been disabled. v ccuv is not latched in this case and when v cc is greater than v ccuv , the fault output returns to the high impedance st ate. the second case shows that dcbus ov has been tripped and that the zero vector mode has been activated. the third case shows that the uvlo for v bs has been tripped and that the highside gate drive output has been disabled. after v bs exceeds the v bsuv threshold , ho will stay low until the hvic input receives a new or rising transition of hin. the fourth case illustrates tha t the itrip trip threshold has been reached and tha t the gate drive outputs have been disabled and a fault has been rep orted through the fault pin (when itrip< v itrip fault returns to high impedance after rcin pin becomes greater than 8v). in the fifth case, the hvic has received a command through the en input to shutdown; as a result, the gate drive outputs have been disabled. the last cas e shows the normal operation of the hvic (a shootthrough prote ction prevention logic prevent lo1,2,3 and ho1,2,3 for each channel turn on simultaneously). vcc dcbus sense vbs itrip en rcin fault lo ho uvlo v cc < v ccuv high 0 0 0 dcbus ov 15 v >ovdcb us high high z 1 0 uvlo v bs 15 v irs26310djpbf www.irf.com ? 2008 international rectifier 27 example 1 example 2 figure 19: noise rejecting input filters figures 20 and 21 present lab data that illustrates the characteristics of the input filters while rec eiving on and off pulses. the input filter characteristic is shown in figure 20; the left side illustrates the narrow pulse on ( short positive pulse) characteristic while the left shows the narrow puls e off (short negative pulse) characteristic. the x axis of figure 20 shows the duration of pw in , while the yaxis shows the resulting pw out duration. it can be seen that for a pw in duration less than t fil,in , that the resulting pw out duration is zero (e.g., the filter rejects the inp ut signal/noise). we also see that once the pw in duration exceed t fil,in , that the pw out durations mimic the pw in durations very well over this interval with the symmetry improving as the du ration increases. to ensure proper operation of th e hvic, it is suggested that the input pulse width for the highs ide inputs be 500 ns. the difference between the pw out and pw in signals of both the narrow on and narrow off cases is shown in figure 21; the careful reader will note the scale o f the yaxis. the xaxis of figure 21 shows the du ration of pw in , while the yaxis shows the resulting pw out Cpw in duration. this data illustrates the performance a nd near symmetry of this input filter. time (ns) figure 20: input filter characteristic irs26310djpbf www.irf.com ? 2008 international rectifier 28 figure 21: difference between the input pulse and t he output pulse integrated bootstrap functionality the new irs26310d family features integrated highv oltage bootstrap mosfets that eliminate the need of the external bootstrap diodes and resistors in many app lications. there is one bootstrap mosfet for each highside ou tput channel and it is connected between the v cc supply and its respective floating supply (i.e., v b1 , v b2 , v b3 ); see figure 22 for an illustration of this intern al connection. the integrated bootstrap mosfet is turned on only d uring the time when lo is high, and it has a limi ted source current due to r bs . the v bs voltage will be charged each cycle depending on th e ontime of lo and the value of the c bs capacitor, the drainsource (collectoremitter) dr op of the external igbt (or mosfet), and the lowsi de free wheeling diode drop. the bootstrap mosfet of each channel follows the st ate of the respective lowside output stage (i.e., the bootstrap mosfet is on when lo is high, it is off when lo is low), unless the v b voltage is higher than approximately 110% of v cc . in that case, the bootstrap mosfet is designed to remain off until v b returns below that threshold; this concept is illustrated in figure 23. v cc v b1 v b2 v b3 figure 22: internal bootstrap mosfet connection fig ure 23: bootstrap mosfet state diagram a bootstrap mosfet is suitable for most of the pwm modulation schemes and can be used either in parall el with the external bootstrap network (i.e., diode and resisto r) or as a replacement of it. the use of the integ rated bootstrap as a replacement of the external bootstrap network may have some limitations. an example of this limitati on may arise when this functionality is used in noncomplementar y pwm schemes (typically 6step modulations) and at very high irs26310djpbf www.irf.com ? 2008 international rectifier 29 pwm duty cycle. in these cases, superior performan ces can be achieved by using an external bootstrap diode in parallel with the internal bootstrap network. bootstrap power supply design for information related to the design of the bootst rap power supply while using the integrated bootstr ap functionality of the irs26310, please refer to application note 1 123 (an1123) entitled bootstrap network analysis: focusing on the integrated bootstrap functionality. this appl ication note is available at www.irf.com . for information related to the design of a standard bootstrap power supply (i.e., using an external di screte diode) please refer to design tip 044 (dt044) entitled using monolithic high voltage gate drivers. this design tip is available at www.irf.com . separate logic and power grounds the irs26310d has separate logic and power ground p in (v ss and com respectively) to eliminate some of the noi se problems that can occur in power conversion applica tions. current sensing shunts are commonly used in many applications for power inverter protection (i.e., o vercurrent protection), and in the case of motor d rive applications, for motor current measurements. in these situations, i t is often beneficial to separate the logic and pow er grounds. figure 24 shows a hvic with separate v ss and com pins and how these two grounds are used in the system. the v ss is used as the reference point for the logic and o vercurrent circuitry; v x in the figure is the voltage between the itrip pin and the v ss pin. alternatively, the com pin is the reference point for the lowside gate drive circuitry. the output voltage used to drive the lowside gate is v lo com; the gateemitter voltage (v ge ) of the lowside switch is the output voltage of the driver minus the drop across r g,lo . v s (x3) hvic ho (x3) v b (x3) lo (x3) com dc+ bus dc bus v cc d bs c bs v ss r g,lo r g,ho v s1 v s2 v s3 r 1 r 2 r 0 v ge1 + v ge2 + v ge3 + itrip v x + figure 24: separate v ss and com pins irs26310djpbf www.irf.com ? 2008 international rectifier 30 tolerant to negative v s transients a common problem in todays highpower switching co nverters is the transient response of the switch no des voltage as the power switches transition on and off quickly while carrying a large current. a typical 3phase inverter circuit is shown in figure 25; here we define the power switch es and diodes of the inverter. if the highside switch (e.g., the igbt q1 in figur es 26 and 27) switches off, while the u phase curre nt is flowing to an inductive load, a current commutation occurs fro m highside switch (q1) to the diode (d2) in parall el with the low side switch of the same inverter leg. at the same instance, the voltage node v s1 , swings from the positive dc bus voltage to the negative dc bus voltage. figure 25: three phase inverter q1 on d2 v s1 q2 off i u dc+ bus dc bus figure 26: q1 conducting figure 27: d2 conducting also when the v phase current flows from the induct ive load back to the inverter (see figures 28 and 2 9), and q4 igbt switches on, the current commutation occurs fr om d3 to q4. at the same instance, the voltage node , v s2 , swings from the positive dc bus voltage to the nega tive dc bus voltage. irs26310djpbf www.irf.com ? 2008 international rectifier 31 figure 28: d3 conducting figure 29: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the ne gative dc bus, rather it swings below the level of the negative dc bus. this undershoot voltage is called negative v s transient. the circuit shown in figure 30 depicts one leg of t he three phase inverter; figures 31 and 32 show a s implified illustration of the commutation of the current betw een q1 and d2. the parasitic inductances in the pow er circuit from the die bonding to the pcb tracks are lumped togeth er in l c and l e for each igbt. when the highside switch is on, v s1 is below the dc+ voltage by the voltage drops asso ciated with the power switch and the parasitic elem ents of the circuit. when the highside power switch turns off , the load current momentarily flows in the lowsid e freewheeling diode due to the inductive load connected to v s1 (the load is not shown in these figures). this cu rrent flows from the dc bus (which is connected to the com pin of the h vic) to the load and a negative voltage between v s1 and the dc bus is induced (i.e., the com pin of the hvic i s at a higher potential than the v s pin). figure 30: parasitic elements figure 31: v s positive figure 32: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 35 v/ns. the negat ive v s transient voltage can exceed this range during some events su ch as short circuit and overcurrent shutdown, when di/dt is greater than in normal operation. international rectifiers hvics have been designed for the robustness required in many of todays dema nding applications. the irs26310d has been seen to withs tand large negative v s transient conditions on the order of 50 v for a period of 50 ns. an illustration of the irs2 6310ds performance can be seen in figure 33. this experiment was conducted using various loads to create this condit ion; the curve shown in this figure illustrates the successful operation of the irs26310d under these stressful co nditions. irs26310djpbf www.irf.com ? 2008 international rectifier 32 figure 33: negative v s transient results for an international rectifier h vic even though the irs26310d has been shown able to ha ndle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layout and component use. pcb layout tips distance between high and low voltage components: its strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. the irs26310d in the plcc44 package has had some unused pins removed in order to maximize the distance between the high vol tage and low voltage pins. please see the case outline plcc44 information in this datasheet for the detai ls. ground plane: in order to minimize noise coupling, the ground pl ane should not be placed under or near the high voltage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 34). in order to reduce the em coupling and improve the power switch turn on/off performance, the gate drive loops must be reduced as much as possible. moreover, curr ent can be injected inside the gate drive loop via the igbt collectortogate parasitic capacitance. the parasi tic autoinductance of the gate loop contributes to developing a voltage across the gateemitter, thus increasing th e possibility of a self turnon effect. figure 34: antenna loops irs26310djpbf www.irf.com ? 2008 international rectifier 33 supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and v ss pins. this connection is shown in figure 35. a ceramic 1 f c eramic capacitor is suitable for most applications. this component should be placed as close as possible to the pins in order to reduce parasitic elements. v cc hin (x3) rcin en itrip v ss fault com lin (x3) lo (x3) ho (x3) v b (x3) v s (x3) c in figure 35: supply capacitor routing and placement: power stage pcb parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the pha se voltage negative transients. in order to avoid such conditions, it is recommended to 1) minimize the highside emitter to lowside collector distance, and 2) minimize th e lowside emitter to negative bus rail stray inductance. how ever, where negative v s spikes remain excessive, further steps may be taken to reduce the spike. this includes pl acing a resistor (5 or less) between the v s pin and the switch node (see figure 36), and in some cases using a cla mping diode between v ss and v s (see figure 37). see dt044 at www.irf.com for more detailed information. figure 36: v s resistor figure 37: v s clamping diode irs26310djpbf www.irf.com ? 2008 international rectifier 34 integrated bootstrap fet limitation the integrated bootstrap fet functionality has an o perational limitation under the following bias cond itions applied to the hvic: ? vcc pin voltage = 0v and ? vs or vb pin voltage > 0 in the absence of a vcc bias, the integrated bootst rap fet voltage blocking capability is compromised and a current conduction path is created between vcc & vb pins, as illustrated in fig.38 below, resulting in power loss and possible damage to the hvic. figure 38: current conduction path between vcc and vb pin relevant application situations: the above mentioned bias condition may be encounter ed under the following situations: ? in a motor control application, a permanent magnet motor naturally rotating while vcc power is off. in this condition, back emf is generated at a motor terminal which causes high voltage bias on vs nodes resulting unwanted current flow to vcc. ? potential situations in other applications where v s/vb node voltage potential increases before the vcc voltage is available (for example due to sequen cing delays in smps supplying vcc bias) application workaround: insertion of a standard pn junction diode between vcc pin of ic and positive terminal of vcc capacito rs (as illustrated in fig.39) prevents current conduction outof vcc pin of gate driver ic. it is important not to connect the vcc capacitor directly to pin of ic. diode sele ction is based on 25v rating or above & current cap ability aligned to icc consumption of ic 100ma should cov er most application situations. as an example, part number # ll4154 from diodes inc (25v/150ma standard diode) can be used. irs26310djpbf www.irf.com ? 2008 international rectifier 35 figure 39: diode insertion between vcc pin and vcc capacitor note that the forward voltage drop on the diode ( v f ) must be taken into account when biasing the vcc p in of the ic to meet uvlo requirements. vcc pin bias = vcc supply voltage C v f of diode . additional documentation several technical documents related to the use of h vics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these docum ents. dt973: managing transients in control ic driven po wer stages an1123: bootstrap network analysis: focusing on th e integrated bootstrap functionality dt044: using monolithic high voltage gate drivers an978: hv floating mosgate driver ics vcc vss (or com) vb vcc capacitor vcc vss (or com) vb vcc capacitor irs26310djpbf www.irf.com ? 2008 international rectifier 36 parameter temperature trends figures 4060 provide information on the experiment al performance of the irs26310d hvic. the line plo tted in each figure is generated from actual lab data. a sm all number of individual samples were tested at thr ee temperatures (40 oc, 25 oc, and 125 oc) in order t o generate the experimental (exp.) curve. the line labeled exp. consist of three data points (one data point at eac h of the tested temperatures) that have been connec ted together to illustrate the understood temperature trend. th e individual data points on the curve were determin ed by calculating the averaged experimental value of the parameter (for a given temperature). 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) ton_lo_1 (ns) exp. figure 40: t on vs. temperature 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) toff_lo_1 (ns) exp. figure 41: t off vs. temperature 0 150 300 450 600 50 25 0 25 50 75 100 125 temperature ( o c) dt (ns) exp. figure 42: dt vs. temperature 0 250 500 750 1000 1250 1500 50 25 0 25 50 75 100 125 temperature ( o c) titrip (ns) exp. figure 43: t itrip vs. temperature irs26310djpbf www.irf.com ? 2008 international rectifier 37 figure 44: t flt vs. temperature figure 45 t en vs. temperature figure 46: r on,rcin vs. temperature figure 47: r on,flt vs. temperature figure 48: i qcc vs. temperature figure 49: i qbs vs. temperature 0 200 400 600 800 1000 50 25 0 25 50 75 100 125 temperature ( o c) titripflt (ns) exp. 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) tfilteren (ns) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) ron_rcin (ohm) exp. 0.00 1.25 2.50 3.75 5.00 50 25 0 25 50 75 100 125 temperature ( o c) iqcc (ma) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) iqbs (ua) exp. 0 20 40 60 80 100 50 25 0 25 50 75 100 125 temperature ( o c) ron_flt (ohm) exp. irs26310djpbf www.irf.com ? 2008 international rectifier 38 figure 50: v ccuv+ vs. temperature figure 51: v ccuv- vs. temperature figure 52: v bsuv+ vs. temperature figure 53: v bsuv- vs. temperature figure 54: v it,th+ vs. temperature figure 55: v it,th- vs. temperature 0.00 0.20 0.40 0.60 0.80 1.00 50 25 0 25 50 75 100 125 temperature (oc) vit_th+ (v) exp. 0.00 0.20 0.40 0.60 0.80 1.00 50 25 0 25 50 75 100 125 temperature (oc) vit_th (v) exp. 0.00 5.00 10.00 15.00 20.00 25.00 50 25 0 25 50 75 100 125 temperature (oc) vbs_1_uv+ (v) exp. 0.00 5.00 10.00 15.00 20.00 25.00 50 25 0 25 50 75 100 125 temperature (oc) vbs_1_uv (v) exp. 0.00 4.00 8.00 12.00 16.00 20.00 50 25 0 25 50 75 100 125 temperature (oc) vcc_uv+ (v) exp. 0.00 4.00 8.00 12.00 16.00 20.00 50 25 0 25 50 75 100 125 temperature (oc) vcc_uv (v) exp. irs26310djpbf www.irf.com ? 2008 international rectifier 39 figure 56: i o+ vs. temperature figure 57: i o- vs. temperature figure 58: v dcbussth+ vs. temperature figure 59: v dcbussth- vs. temperature figure 60: i itrip+ vs. temperature 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) io+_lo_1 (ma) exp. 0 100 200 300 400 500 50 25 0 25 50 75 100 125 temperature ( o c) io_lo_1 (ma) exp. 0.00 2.00 4.00 6.00 8.00 10.00 50 25 0 25 50 75 100 125 temperature ( o c) itrip_1 (ua) exp. irs26310djpbf www.irf.com ? 2008 international rectifier 40 package details: plcc44 irs26310djpbf www.irf.com ? 2008 international rectifier 41 tape and reel details: plcc44 carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial e f a c d g a b h note : controlling dim ension in m m loaded tape feed direction a h f e g d b c irs26310djpbf www.irf.com ? 2008 international rectifier 42 part marking information irs26310djpbf www.irf.com ? 2008 international rectifier 43 ordering information standard pack base part number package type form quantity complete part number tube/bulk 27 irs26310djpbf irs26310d plcc44 tape and reel 500 irs26310djtrpbf the information provided in this document is believ ed to be accurate and reliable. however, internatio nal rectifier assumes no responsibility for the consequences of the use of this information . international rectifier assumes no responsibilit y for any infringement of patents or of other rights of third parties which may result from the use of this information. no license is grante d by implication or otherwise under any patent or patent rights of international rectifier. the specifications mentioned in this document are subject to change without notice. this document supersedes and replaces all information pr eviously supplied. for technical support, please contact irs technica l assistance center http://www.irf.com/technicalinfo/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 2527105 irs26310djpbf www.irf.com ? 2007 international rectifier 44 revision history revision date change comments 1.6 041708 corrected unit for deadtime from us to ns 1.7 041808 updated qualification information table per new ir standard 1.8 060111 add bootstrap fet limitation |
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